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ISL97671
TABLE 3. OPERATING MODES SELECTED BY DEVICE CONTROL
REGISTER BITS 1 AND 2
Fault/Status Register (0x02)
This register has 6 status bits that allow monitoring of the backlight
PWM_MD
X
1
0
PWM_SEL
1
0
0
MODE
PWM Mode
SMBus/I 2 C Mode
SMBus/I 2 C and PWM Mode with DPST
controller’s operating state. Bit 0 is a logical “OR” of all fault codes to
simplify error detection. Not all of the bits in this register are fault
related (Bit 3 is a simple BL status indicator). The remaining bits are
reserved and return a “0” when read and ignore the bit value when
written. All of the bits in this register are read-only, with the
exception of bit 0, which can be cleared by writing to it.
The PWM_SEL bit determines whether the SMBus/I 2 C or PWM
input should drive the output brightness in terms of PWM
dimming. When PWM_SEL bit is 1, the PWM drives the output
brightness regardless of what the PWM_MD is.
When the PWM_SEL bit is 0, the PWM_MD bit selects the
manner in which the PWM dimming is to be interpreted; when
this bit is 1, the PWM dimming is based on the SMBus/I 2 C
brightness setting. When this bit is 0, the PWM dimming reflects
a percentage change in the current brightness programmed in
the SMBus/I 2 C Register 0x00, i.e. DPST (Display Power Saving
Technology) mode as:
DSPT Brightness = Cbt × PWM (EQ. 16)
Where:
Cbt = Current brightness setting from SMBus/I 2 C Register 0x00
without influence from the PWM
PWM = is the percent duty cycle of the PWM
For example, the Cbt = 50% duty cycle programmed in the
SMBus/I 2 C Register 0x00 and the PWM frequency is tuned to be
200Hz with an appropriate capacitor at the FPWM pin. On the other
hand, PWM is fed with a 1kHz 30% high PWM signal. When
PWM_SEL = 0 and PWM_MD = 0, the device is in DPST operation
where DPST brightness = 15% PWM dimming at 200Hz.
20
? A Read Byte cycle to Register 0x02 indicates the current BL
on/off status in BL_STAT (1 if the BL is on, 0 if the BL is off).
? A Read Byte cycles to Register 0x2 also returns FAULT as the
logical OR of THRM_SHDN, OV_CURR, 2_CH_SD, and 1_CH_SD
should these events occur.
? 1_CH_SD returns a 1 if one or more channels have faulted out.
? 2_CH_SD returns a 1 if two or more channels have faulted out.
? A fault will not be reported in the event that the BL is
commanded on and then immediately off by the system.
? When FAULT is set to 1, it will remain at 1 even if the signal
which sets it goes away. FAULT will be cleared when the
BL_CTL bit of the Device Control Register is toggled or when
written low. At that time, if the fault condition is still present or
reoccurs, FAULT will be set to 1 again. BL_STAT will not cause
FAULT to be set .
? The default value for Register 0x02 is 0x00.
Identification Register (0x03)
The ID register contains 3 bit fields to denote the LED driver (always
set to 1), manufacturer and the silicon revision of the controller IC.
The bit field widths allow up to 16 vendors with up to 8 silicon
revisions each. In order to keep the number of silicon revisions low,
the revision field will not be updated unless the part will make it out
to the user’s factory. Thus, if during the engineering development
process, 3 silicon spins were needed, the next available revision ID
would be used for all 3 spins until that same ID made it to the
factory. Except Bit 7, which has to be 1, all of the bits in this register
are read-only.
? Vendor ID 9 represents Intersil Corporation.
? The default value for Register 0x03 is 0xC8.
The initial value of REV shall be 0. Subsequent values of REV will
increment by 1.
FN7631.3
August 14, 2012
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